v ishay siliconix spice device model SI8429DB p-channel 1.2v (g-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 5-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www. vi s h a y .com document number: 69660 s-80009 ? rev . a, 21-jan-08
vishay siliconix spice device model SI8429DB specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n simulated data measu red data unit static gate threshold voltage v gs(t h ) v ds = v gs , i d = ? 250 a 0 . 6 0 v drain-source on-state resistance a r d s (on) v gs = ? 4.5 v, i d = ? 1 a 0 . 0 3 1 0 . 0 2 9 a v gs = ? 2.5 v, i d = ? 1 a 0 . 0 3 6 0 . 0 3 5 v gs = ? 1.8 v, i d = ? 1 a 0 . 0 4 3 0 . 0 4 3 v gs = ? 1.5 v, i d = ? 1 a 0 . 0 4 9 0 . 0 5 1 drain-source on-state resistance a r d s (on) v gs = ? 1.2 v, i d = ? 1 a 0 . 0 6 6 0 . 0 6 5 ? forw ard transconductance a g fs v ds = ? 4 v, i d = ? 1 a 1 0 s diode forw ard voltage a v sd i s = ? 1 a, v gs = 0 v ? 0.60 ? 0.70 v dy namic b input capacitance c iss 1 7 9 3 1 6 4 0 output capacitance c oss 5 8 8 5 9 0 rev e rse transfe r capacitance c rs s v ds = ? 4 v, v gs = 0 v, f = 1 m h z 3 7 9 3 8 0 pf v ds = ? 4 v, v gs = ? 5 v, i d = ? 1 a 1 8 2 4 total gate charge q g 1 6 2 1 gate-source charge q gs 1 . 8 1 . 8 gate-drain charge q gd v ds = ? 4 v, v gs = ? 4.5 v, i d = ? 1 a 3 . 7 3 . 7 nc not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. 2 www. vi s h a y .com document number: 69660 s-80009 ? rev . a , 21-jan-08
v ishay siliconix spice device model SI8429DB comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) 3 www. vi s h a y .com document number: 69660 s-80009 ? rev . a , 21-jan-08
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